1. Field of the Invention
Embodiments of the invention relate generally to data processing techniques and related implementations for digital modulators. More particularly, embodiments of the invention relate to multiplier-less data processing techniques and related implementations adapted to reduce the amount of space and/or power required to generate and process phase and amplitude data in digital polar modulators.
A claim of priority is made to Korean Patent Application No. 2006-0104914 filed on Oct. 27, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Portable electronic devices continue to become smaller, faster, and more powerful with each new generation. For example, cutting-edge cellular phones and personal digital assistants (PDAs) are typically capable of efficiently processing and transmitting high quality voice, audio, video, text, and so on, whereas previous generations of these devices were relatively less efficient at processing and transmitting these types of data. In order to take advantage of the enhanced capabilities of modern portable electronic devices, researchers have developed new standards for more efficiently coding and processing data in the devices and for transmitting data between the devices.
One example of such a standard is the Enhanced Data rates for Global System for Mobile communications (GSM) Evolution (EDGE) standard. The EDGE standard was developed to provide high data rate transmission for portable electronic devices such as cellular phones. In order to achieve the high data rate, the EDGE standard uses simultaneous amplitude modulation (AM) and phase modulation (PM). For instance, in one example, the EDGE standard uses 3π/8-shifted eight-phase-shift keying (3π/8-8PSK) polar modulation.
To illustrate one possible implementation of the EDGE standard, FIG. 1 shows a block diagram of one type of conventional EDGE base-band modulator. Referring to FIG. 1, a conventional EDGE base-band modulator 100 comprises a 3-bit symbol mapper 101, a rotation counter 102, an adder 109, an I-Q mapper 103, an up sampler 104, pulse shape filters 105, a coordinate rotation digital computer (CORDIC) processor 106, an un-wrapper 107, and a derivative calculator 108.
3-bit symbol mapper 101 receives an input digital data stream (“bit stream”) and maps the bit stream onto a plurality of 3-bit symbols. Rotation counter 102 generates phase data according to 3π/8 rotation as defined by the EDGE standard. Adder 109 combines the 3-bit symbols from 3-bit symbol mapper 101 with the phase data generated by rotation counter 102 to produce an input signal for I-Q mapper 103. I-Q mapper 103 receives the input signal and generates real and imaginary coordinates (i.e., rectangular coordinates) based on the input signal. The real coordinates will be referred to as I-data and the imaginary coordinates will be referred to as Q-data.
Up sampler 104 receives the I-data and the Q-data generated by I-Q mapper 103 and up-samples the I-data and the Q-data by 96 times (96×) to output data with a desired resolution based on an operating frequency of CORDIC processor 106. Pulse shape filters 105 receive the respective up-sampled I-data and Q-data and generates respective pulse trains representing the up-sampled I-data and Q-data.
CORDIC processor 106 receives the respective pulse trains representing the up-sampled I-data and Q-data and converts the pulse trains into amplitude and phase data. Un-wrapper 107 then performs an unwrapping function on the phase data to produce unwrapped phase data. Briefly, the unwrapping function removes discontinuities from the phase data to allow differentiation of the phase data. Finally, derivative calculator 108 differentiates the unwrapped phase data to generate frequency data.
In the example of FIG. 1, the I-data and Q-data are up-sampled by 96× to produce amplitude and phase data with an appropriate resolution for use in a system having an operating frequency of 26 MHz. For example, in certain types of two-point digital phase lock loop (PLL) modulators, base-band modulator output data is required to be generated at 26 MHz. In the case of the base-band modulator of FIG. 1, this high data rate is generated by 96× over-sampling of an input data stream.
In systems requiring base-band modulator output data to be generated at high rates such as 26 MHz, features such as pulse shape filters 105, CORDIC processor 106, un-wrapper 107, and derivative calculator 108 are typically designed to operate at these high rates. Moreover, these high operating rates tend to significantly influence the design of these features.
For example, EDGE base band modulators often use pulse shape filters with a length of 4 symbols. Accordingly, where 96× over-sampling and a 26 MHz operating frequency are used, each of pulse shape filters 105 will include 96*4=384 filter taps, each designed to use a 26 MHz clock.
As another example, where CORDIC processor 106 operates at 26 MHz, hardware performance limitations may preclude CORDIC processor 106 from using an iterative algorithm to compute amplitude and phase data from I-data and Q-data because the iterative algorithm may not be fast enough to generate output data at 26 MHz. As a result, CORDIC processor 106 may include multiple sequential stages, occupying a significantly larger amount of chip area and using significantly more power compared with a functionally similar, but slower CORDIC processor using an iterative algorithm.
Due to these and other drawbacks of high speed base-band modulators such as that illustrated in of FIG. 1, it would be desirable to create a base-band modulator capable of implementing algorithms in a more power and space efficient manner.